Background and Objectives: In this paper, a novel structure as a folded-Mirror (FM) Trans-impedance Amplifier (TIA) is designed and introduced for the first time based on the combination of the current-mirror and the folded-cascade topologies. The trans-impedance amplifier stage is the most critical building block in a receiver system. This novel proposed topology is based on the combination of the current mirror topology and the folded-cascade topology, which is designed using active elements. The idea is to use a current mirror topology at the input node. In the proposed circuit, unlike many other reported designs, the signal current (and not the voltage) is being amplified till it reaches the output node. The proposed TIA benefits from a low input resistance, due to the use of a diode-connected transistor, as part of the current mirror topology, which helps to isolate the dominant input capacitance. So, as a result, the data rate of 5Gbps is obtained by consuming considerably low power. Also, the designed circuit employs only six active elements, which yields a small occupied chip area, while providing 40.6dBΩ of trans-impedance gain, 3.55GHz frequency bandwidth, and 664nArms input-referred noise by consuming only 315µW power using a 1V supply. Results justify the proper performance of the proposed circuit structure as a low-power TIA stage.Methods: The proposed topology is based on the combination of the current mirror topology and the folded-cascade topology. The circuit performance of the proposed folded-mirror TIA is simulated using 90nm CMOS technology parameters in the Hspice software. Furthermore, the Monte-Carlo analysis over the size of widths and lengths of the transistors is performed for 200runs, to analyze the fabrication process.Results: The proposed FM TIA circuit provides 40.6dBΩ trans-impedance gain and 3.55GHz frequency bandwidth, while, consuming only 315µW power using a 1V supply. Besides, as analyzing the quality of the output signal in the receiver circuits for communication applications is vital, the eye-diagram of the proposed FM TIA for a 50µA input signal is opened about 5mV, while, for a 100µA input signal the eye is opened vertically about 10mV. So, the vertical and horizontal opening of the eye is clearly shown. Furthermore, Monte-Carlo analysis over the trans-impedance gain represents a normal distribution with the mean value of 40.6dBΩ and standard deviation of 0.4dBΩ. Also, the value of the input resistance of the FM TIA is equal to 84.4Ω at low frequencies and reaches the value of 75Ω at -3dB frequency. The analysis of the effect of the feedback network on the value of the input resistance demonstrates the input resistance in the absence of the feedback network reaches up to 1.4MΩ, which yields the importance of the existence of the feedback network to obtain a broadband system.Conclusion: In this paper, a trans-impedance amplifier based on a combination of the current-mirror topology and the folded-cascade topology is presented, which amplifies the current signal and converts it to the voltage at the output node. Due to the existence of a diode-connected transistor at the input node, the input resistance of the TIA is comparatively small. Furthermore, four out of six transistors are PMOS transistors, which represent less thermal noise in comparison with NMOS transistors. Also, the proposed folded-Mirror topology occupies a relatively small area on-chip, due to the fact that no passive element is used in the feedforward network. Results using 90nm CMOS technology parameters show 40.6dBΩ trans-impedance gain, 3.55GHz frequency bandwidth, 664nArms input-referred noise, and only 315µW power dissipation using a 1volt supply, which indicates the proper performance of the proposed circuit as a low-power building block.

A novel gain boosted folded cascode Op-Amp using simple single stage auxiliary amplifiers is presented. The proposed auxiliary amplifiers are designed in a way that have proper input and output DC common mode voltage without using common mode feedback network. The inputs of the auxiliary amplifiers are insulated by the coupling capacitors and floating-gate MOS transistors. Thus, the DC input voltage level limit has been removed. Diode connected transistors are also used in the output of the auxiliary amplifiers, which keep the output voltage level at the desired. A simple single stage auxiliary amplifier imposes fewer poles and zeroes on the main amplifier compared to more complicated amplifiers where consumes also less power consumption. Simulation results in a 0.18μm CMOS technology show a DC gain enhancement of about 20dB while output swing, slew rate, settling time, phase margin and gain-bandwidth retain almost as the same as previous folded cascode design.

Design and simulation results of fully integrated 5-GHz CMOS LNAs are presented in this paper. Three different input impedance matching techniques are considered. Using a simple L-C network, the parasitic input resistance of a MOSFET is converted to a 50Ω resistance. As it is analytically proven, that is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFET’s input resistance. The effect of each input impedance matching on the amplifier’s noise figure and gain is discussed. By employing the folded cascode configuration, these LNAs can operate at a reduced supply voltage and thus lower power consumption. To address the issue of nonlinearity in design of low voltage LNAs, a new linearization technique is employed. As a result, the IIP3 is improved extensively without sacrificing other parameters. These LNAs consume 1.3 mW power under a 0.6 V supply voltage.

A double recycling Op-Amp based on a simple recycling folded cascode Op-Amp is presented. The proposed Op-Amp has significantly improved performance compared to a recycling folded cascode. In the proposed Op-Amp, those cascode output current sources of recycling folded cascode that still have a constant value have been considered and have taken on a dynamic state through capacitive couplings in the path created between the input and output of the amplifier. DC gain, unity-gain bandwidth, and slew rate have been improved compared to the previous amplifier at the same power consumption. Simulation results using the 0. 18μ m CMOS technology show a DC gain enhancement of 6dB, 35% improvement in slew rate, and almost a 30% increase the bandwidth compared to the traditional recycling folded cascode Op-Amp. Also, smaller input-referred noise is achieved. Simulated results of proposed circuit show the values of SR, power consumption and DC gain are about 93. 5 V/µ s, 1. 02mW and 68. 3 dB respectively.

This article proposed a simple self cascode RGC amplifier configuration to increase the gain and bandwidth. The cascode amplifier eliminates the miller capacitance between input and output and facilitates high gain, high input and output impedance with high bandwidth. However, the cascode amplifier requires relatively high supply voltage for proper operation and it decreases the output voltage swing by overdrive voltage. These issues are overcome by self cascode based RGC amplifier; even though it has low bandwidth due to the presence of one of its pole at low frequency. The bandwidth and output impedance of the conventional RGC has increased using a split length compensation technique. To improve the overall performance of the amplifier, introduced a simple self cascode RGC without using additional passive elements. The expression of gain and output impedance for the proposed amplifier is derived using small signal analysis. The calculated value of voltage gain for the projected circuit is 58. 37 dB which is more than the self cascode based RGC. The power dissipation of the proposed circuit is 1. 07 μ Watt and it was compared with CS, cascode, self cascode and SC based cascode, RGC, SC based RGC amplifiers.

This paper presents a wide input voltage range negative impedance converter (NIC) circuit operating in weak inversion. A small signal analysis has been performed, resulting in a circuit model that characterises the input impedance function, Zin(s). A boosted folded cascode (BFC) OTA is presented using the proposed NIC. Incorporating the proposed NIC at the output node of a folded cascode (FC) OTA, the output impedance is increased, resulting in a noticeable improvement in the overall voltage gain without phase margin (PM) degrading. Post-layout simulation is performed using standard 180nm CMOS technology, while the two essential large resistors of the proposed NIC are considered off-chip components. The boosted OTA exhibits a DC gain improvement of 17 dB with no PM degradation over a conventional FC OTA at the expense of 1.5% more power consumption. The proposed NIC circuit can be incorporated easily into any boosted OTA realized by alternative methods. Based on this concept, a double-boosted OTA is also introduced.

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A dual band monopole antenna for passive RFID tags is presented, simulated with suitable bandwidth and gain for RFID application. The monopole is optimized using HFSS to obtain dual band characteristics. This paper presents a dual-band monopole antenna suitable for passive RFID applications which operates at 2.45 GHz and 5.8 GHz. This antenna is designed with low cost and low profile substrate to achieve a reasonable gain. This antenna has a total area of 38×28mm2 and is mounted on an FR4 substrate with a thickness of 1.6mm, dielectric permittivity constant 4.4, and loss tangent of 0.025.